1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a subtractor circuit.
2. Description of the Prior Art
Subtractor circuits find a wide variety of uses in the electronics industry, where the difference between two values is needed. For instance, subtractors are used in conjunction with high speed comparators in high speed flag logic for FIFO (First in First Out) memories. Subtractor circuits can also be used in arithmetic logic units (ALU's), found in PCs and other computers, to alert the system when the difference between two numbers exceeds a certain value.
Serial borrow propagation subtractors are a common form of subtractor circuits. They contain a number of full subtractors, each of which is capable of determining the difference between any two binary bits of data. With only a borrow input and two value inputs, a full subtractor can determine the difference between the two values. The full subtractor also produces a borrow output which is used as an input to the next full subtractor. Because of this propagation of the borrow signal from the output of one full subtractor to the input of the next full subtractor, the subtractors are said to be serially connected to one another.
The serial propagation of a borrow signal through many full subtractors can be very time consuming. Consider determining the difference between two sixteen bit numbers. The first subtractor determines the difference between the LSBs (Least Significant Bits) of the two numbers, generating a borrow output resulting from the subtraction operation. This borrow output value is used as the borrow input of the next full subtractor. The borrow input, along with the next two bits, LSB+1, are needed to perform the subtraction which generates the next borrow output value. This serial propagation process is continued until the difference between the last two bits, the MSBs (most significant bits), is determined. In each case, subtraction between two bits cannot occur until a borrow signal from the previous full subtractor is available. In addition to borrow propagation delays, there are gate delays between each successive full subtractor as well as required buffering circuitry. It is well known in the art that such a serial borrow propagation subtractor can be very slow.
The slow speed of serial borrow propagation subtractors can have an adverse effect on overall system performance. For instance, the speed of subtractors used in FIFO (First In First Out) memory applications is important. A FIFO flag tells the user how full the FIFO is. Flag logic, which is dependent on an internal subtractor, must be generated quickly. If the subtractor is slow, it will have an adverse affect on how quickly the flag logic can be generated.
Typically, the difference output of a serial borrow propagation subtractor is input to a comparator. The borrow propagates through the next full subtractor at the same time the comparator is performing its function. It is common for a comparator to complete its task much more quickly than can a serial borrow propagation subtractor; this necessitates the comparator spend idle time waiting for the subtractor to finish its task. In this instance, the serial borrow propagation subtractor delay becomes a bottle neck to the overall system performance. It therefore becomes desirable to speed up the borrow function so that an overall increase in system performance is realized.
A fundamental way to speed up the subtractor and therefore increase overall system performance is to minimize propagation delays caused by the purely serial borrow propagation from full subtractor to full subtractor. It would be desirable to accomplish this using current full subtractor design.